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Message-ID: <20070809083055.GA19048@gondor.apana.org.au>
Date: Thu, 9 Aug 2007 16:30:55 +0800
From: Herbert Xu <herbert.xu@...hat.com>
To: Chris Snook <csnook@...hat.com>
Cc: akpm@...ux-foundation.org, torvalds@...ux-foundation.org,
ak@...e.de, heiko.carstens@...ibm.com, davem@...emloft.net,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
schwidefsky@...ibm.com, wensong@...ux-vs.org, horms@...ge.net.au,
wjiang@...ilience.com, cfriesen@...tel.com, zlynx@....org
Subject: Re: [PATCH] make atomic_t volatile on all architectures
On Thu, Aug 09, 2007 at 03:47:57AM -0400, Chris Snook wrote:
>
> If they're not doing anything, sure. Plenty of loops actually do some sort
> of real work while waiting for their halt condition, possibly even work
> which is necessary for their halt condition to occur, and you definitely
> don't want to be doing cpu_relax() in this case. On register-rich
> architectures you can do quite a lot of work without needing to reuse the
> register containing the result of the atomic_read(). Those are precisely
> the architectures where barrier() hurts the most.
I have a problem with this argument. The same loop could be
using a non-atomic as long as the updaters are serialised. Would
you suggest that we turn such non-atomics into volatiles too?
Any loop that's waiting for an external halt condition either
has to schedule away (which is a barrier) or you'd be busy
waiting in which case you should use cpu_relax.
Do you have an example where this isn't the case?
Cheers,
--
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@...dor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
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