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Date:	Tue, 21 Aug 2007 13:37:51 +0200
From:	Andi Kleen <ak@...e.de>
To:	Paul Mackerras <paulus@...ba.org>
Cc:	Russell King <rmk+lkml@....linux.org.uk>,
	Segher Boessenkool <segher@...nel.crashing.org>,
	Christoph Lameter <clameter@....com>,
	heiko.carstens@...ibm.com, horms@...ge.net.au,
	linux-kernel@...r.kernel.org,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>, ak@...e.de,
	netdev@...r.kernel.org, cfriesen@...tel.com,
	akpm@...ux-foundation.org, rpjday@...dspring.com,
	Nick Piggin <nickpiggin@...oo.com.au>,
	linux-arch@...r.kernel.org, jesper.juhl@...il.com,
	satyam@...radead.org, zlynx@....org, schwidefsky@...ibm.com,
	Chris Snook <csnook@...hat.com>,
	Herbert Xu <herbert@...dor.apana.org.au>, davem@...emloft.net,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	wensong@...ux-vs.org, wjiang@...ilience.com
Subject: Re: [PATCH 0/24] make atomic_read() behave consistently across all architectures

On Tue, Aug 21, 2007 at 07:33:49PM +1000, Paul Mackerras wrote:
> So the whole discussion is irrelevant to ARM, PowerPC and any other
> architecture except x86[-64].

It's even irrelevant on x86 because all modifying operations on atomic_t 
are coded in inline assembler and will always be RMW no matter
if atomic_t is volatile or not.

[ignoring atomic_set(x, atomic_read(x) + 1) which nobody should do]

The only issue is if atomic_t should have a implicit barrier or not.
My personal opinion is yes -- better safe than sorry. And any code
impact it may have is typically dwarved by the next cache miss anyways,
so it doesn't matter much.

-Andi

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