linux-kernel - Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR

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Message-ID: <20070921103120.GK2367@kernel.dk>
Date:	Fri, 21 Sep 2007 12:31:20 +0200
From:	Jens Axboe <jens.axboe@...cle.com>
To:	Peer Chen <peerchen@...il.com>
Cc:	linux-kernel <linux-kernel@...r.kernel.org>,
	jeff <jeff@...zik.org>, akpm <akpm@...ux-foundation.org>,
	linux-ide <linux-ide@...r.kernel.org>
Subject: Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR

On Fri, Sep 21 2007, Peer Chen wrote:
> According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> by software when GHC.AE is set to ¡®1¡¯.
> 
> Signed-off-by: Peer Chen <peerchen@...il.com>
> ---
> --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig	2007-09-20 11:01:55.000000000 -0400
> +++ linux-2.6.23-rc7/drivers/ata/ahci.c	2007-09-20 11:07:31.000000000 -0400
> @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct 
>  	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
>  	u32 tmp;
>  
> +        /* turn on AHCI mode before controller reset*/
> +        writel(HOST_AHCI_EN, mmio + HOST_CTL);
> +        (void) readl(mmio + HOST_CTL);  /* flush */
> +
>  	/* global controller reset */
>  	tmp = readl(mmio + HOST_CTL);
>  	if ((tmp & HOST_RESET) == 0) {

I appreciate the readl() flushes, but in this particular case we end up
reading the exact offset again below.

-- 
Jens Axboe

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