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Message-ID: <20071004052153.GA15131@wotan.suse.de> Date: Thu, 4 Oct 2007 07:21:54 +0200 From: Nick Piggin <npiggin@...e.de> To: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, Linus Torvalds <torvalds@...ux-foundation.org>, Andi Kleen <ak@...e.de> Subject: [rfc][patch 1/3] x86_64: fence nontemproal stores Hi, Here's a couple of patches to improve the memory barrier situation on x86. They probably aren't going upstream until after the x86 merge, however I'm posting them here for RFC, and in case anybody wants to backport into stable trees. --- movnt* instructions are not strongly ordered with respect to other stores, so if we are to assume stores are strongly ordered in the rest of the x86_64 kernel, we must fence these off (see similar examples in i386 kernel). [ The AMD memory ordering document seems to say that nontemporal stores can also pass earlier regular stores, so maybe we need sfences _before_ movnt* everywhere too? ] Signed-off-by: Nick Piggin <npiggin@...e.de> Index: linux-2.6/arch/x86_64/lib/copy_user_nocache.S =================================================================== --- linux-2.6.orig/arch/x86_64/lib/copy_user_nocache.S +++ linux-2.6/arch/x86_64/lib/copy_user_nocache.S @@ -117,6 +117,7 @@ ENTRY(__copy_user_nocache) popq %rbx CFI_ADJUST_CFA_OFFSET -8 CFI_RESTORE rbx + sfence ret CFI_RESTORE_STATE - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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