lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20071004.101153.28792915.hyoshiok@miraclelinux.com>
Date:	Thu, 04 Oct 2007 10:11:53 +0900 (JST)
From:	Hiro Yoshioka <hyoshiok@...aclelinux.com>
To:	torvalds@...ux-foundation.org
Cc:	penberg@...helsinki.fi, neil@...ig.demon.co.uk,
	linux-kernel@...r.kernel.org, akpm@...ux-foundation.org,
	hyoshiok@...aclelinux.com
Subject: Re: File corruption when using kernels 2.6.18+

Hi,

From: Linus Torvalds <torvalds@...ux-foundation.org>
> On Wed, 3 Oct 2007, Pekka Enberg wrote:
> > 
> > On 10/3/07, Linus Torvalds <torvalds@...ux-foundation.org> wrote:
> > > I would bet that the reason the intel-optimized memcpy triggers this is
> > > that the non-temporal stores just means that you go out directly on the
> > > bus, and it probably just shows a weakness in the chipset or bus that
> > > doesn't show with the normal cacheline accesses.
> > 
> > But that should show up with memtest too, no?
> 
> Not unless memtest uses non-temporal stores with the same (or similar) 
> access patterns.
> 
> The thing is, the CPU cache hides a *lot* of activity from the chipset, 
> and changes the access patterns radically. 
> 
> With normal cached accesses, you'd normally see just the "fill cacheline" 
> and "write out cacheline" pattern. With movnt, you'd see non-cacheline 
> accesses to memory. If the chipset was tested under mostly normal loads, 
> the movnt cases have been getting a lot less coverage.

I'm not so sure whether it is chipset's bug or not.

The movnt does have the WC (write combining) semantics and
bypass the hardware cache to store the data.

http://www.intel.com/products/processor/manuals/index.htm

Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 1: Basic Architecture

Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3A: System Programming Guide

Thanks in advance,
  Hiro
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists