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Message-ID: <653FFBB4508B9042B5D43DC9E18836F501797305@scsmsx415.amr.corp.intel.com>
Date: Thu, 4 Oct 2007 21:37:41 -0700
From: "Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>
To: "Thomas Gleixner" <tglx@...utronix.de>, "Andi Kleen" <ak@...e.de>
Cc: "Arjan van de Ven" <arjan@...radead.org>,
"David Bahi" <dbahi@...ell.com>,
"LKML" <linux-kernel@...r.kernel.org>,
<linux-rt-users@...r.kernel.org>,
"Andrew Morton" <akpm@...ux-foundation.org>,
"Ingo Molnar" <mingo@...e.hu>,
"Gregory Haskins" <GHaskins@...ell.com>
Subject: RE: nmi_watchdog fix for x86_64 to be more like i386
>-----Original Message-----
>From: linux-kernel-owner@...r.kernel.org
>[mailto:linux-kernel-owner@...r.kernel.org] On Behalf Of
>Thomas Gleixner
>Sent: Monday, October 01, 2007 11:19 PM
>To: Andi Kleen
>Cc: Arjan van de Ven; David Bahi; LKML;
>linux-rt-users@...r.kernel.org; Andrew Morton; Ingo Molnar;
>Gregory Haskins
>Subject: Re: nmi_watchdog fix for x86_64 to be more like i386
>
>>
>> The only workaround for chipsets ignoring IRQ affinity would
>be to keep
>> track on which CPU irq 0 happens and then restart APIC timer
>interrupts
>> on the others (or send IPIs) as needed. But that would be
>fairly ugly.
>
>The clock events code does handle this already. The broadcast
>interrupt
>can come in on any cpu. It's just the nmi watchdog which would
>be affected
>by that.
>
Probably we can workaround this by keeping track of IRQ0 count at percpu
level and
use local apic timer + this percpu counter in NMI. Or just increment
local
apic timer count in IRQ0 with nohz enabled.
Thanks,
Venki
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