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Message-ID: <20071017122842.GB14401@wotan.suse.de>
Date: Wed, 17 Oct 2007 14:28:42 +0200
From: Nick Piggin <npiggin@...e.de>
To: Herbert Xu <herbert@...dor.apana.org.au>
Cc: mikulas@...ax.karlin.mff.cuni.cz, arjan@...radead.org,
linux-kernel@...r.kernel.org,
virtualization <virtualization@...ts.linux-foundation.org>
Subject: Re: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers)
On Wed, Oct 17, 2007 at 01:51:17PM +0800, Herbert Xu wrote:
> Nick Piggin <npiggin@...e.de> wrote:
> >
> > Also, for non-wb memory. I don't think the Intel document referenced
> > says anything about this, but the AMD document says that loads can pass
> > loads (page 8, rule b).
> >
> > This is why our rmb() is still an lfence.
>
> BTW, Xen (in particular, the code in drivers/xen) uses mb/rmb/wmb
> instead of smp_mb/smp_rmb/smp_wmb when it accesses memory that's
> shared with other Xen domains or the hypervisor.
>
> The reason this is necessary is because even if a Xen domain is
> UP the hypervisor might be SMP.
>
> It would be nice if we can have these adopt the new SMP barriers
> on x86 instead of the IO ones as they currently do.
That's a good point actually. Something like raw_smp_*mb, which
always orders memory, but only for regular WB operatoins. I could
put that on the todo list...
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