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Message-ID: <18200.63696.399763.437303@zeus.sw.starentnetworks.com>
Date: Fri, 19 Oct 2007 14:34:56 -0400
From: Dave Johnson <djohnson+linux-kernel@...starentnetworks.com>
To: Hiroshi Shimamoto <h-shimamoto@...jp.nec.com>
Cc: Ingo Molnar <mingo@...e.hu>, linux-kernel@...r.kernel.org,
Thomas Gleixner <tglx@...utronix.de>, Greg KH <gregkh@...e.de>,
Chris Wright <chrisw@...s-sol.org>
Subject: Re: [PATCH] i386: fix TSC clock source calibration error [part 2]
Hiroshi Shimamoto writes:
> Dave Johnson wrote:
> > mach_prepare_counter();
>
> It's a really rare case, but if SMI interrupt takes CPU here, just after
> prepare and before rdtscll, it makes delta64 shorter than expected one.
> Is it possible? And how about moving rdtscll before mach_prepare_counter()?
>
> > rdtscll(start);
Yep, rare indeed (about 1 instruction). Moving the start read before
the prepare call should solve that one too providing the setup doesn't
take any real measurable time.
--
Dave Johnson
Starent Networks
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