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Message-Id: <1193688778.4723.35.camel@koto.keithp.com>
Date:	Mon, 29 Oct 2007 13:12:58 -0700
From:	Keith Packard <keithp@...thp.com>
To:	Jesse Barnes <jesse.barnes@...el.com>
Cc:	keithp@...thp.com, dri-devel@...ts.sourceforge.net,
	Dave Airlie <airlied@...net.ie>, linux-kernel@...r.kernel.org,
	dri-devel@...ts.sf.net
Subject: Re: [RFC] AGP initial support for chipset flushing..


On Mon, 2007-10-29 at 12:47 -0700, Jesse Barnes wrote:

> In this case, we're performing basically a dma_sync*(...DMA_TO_DEVICE) 
> right?

But this is just for the GPU; every other DMA device in the system is
cache-coherent.

>   Can we be sure that a single flush is sufficient?  Is there any 
> window between when we flush and when we start accessing memory with 
> the device that we could get into more caching trouble?

An uncached write to this page will not complete until the buffers are
completely flushed.

> Looks reasonable, I'm not sure we can do much better.  The only concern 
> I have is that allocating some more PCI space like that may end up 
> clobbering some *other* hidden BIOS mapping, but there's not a whole 
> lot we can do about that.

This isn't a hidden mapping; the i965 doesn't allocate space for it in
the BIOS.

-- 
keith.packard@...el.com

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