linux-kernel - RE: [patch 0/2] x86, ptrace: support for branch trace store(BTS)

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <029E5BE7F699594398CA44E3DDF554440108FE48@swsmsx413.ger.corp.intel.com>
Date:	Mon, 3 Dec 2007 15:17:47 -0000
From:	"Metzger, Markus T" <markus.t.metzger@...el.com>
To:	"Roland McGrath" <roland@...hat.com>,
	"Andrew Morton" <akpm@...ux-foundation.org>
Cc:	"Andi Kleen" <ak@...e.de>, <tglx@...utronix.de>,
	<linux-kernel@...r.kernel.org>, <hpa@...or.com>,
	"Siddha, Suresh B" <suresh.b.siddha@...el.com>,
	"Michael Kerrisk" <mtk-manpages@....net>,
	<markus.t.metzger@...il.com>, "Ingo Molnar" <mingo@...e.hu>,
	"Markus Metzger" <markus.t.metzger@...glemail.com>
Subject: RE: [patch 0/2] x86, ptrace: support for branch trace store(BTS)

>There seems to be support for block stepping in arch/x86/kernel/step.c,
>which is used by kernel/ptrace.c.
>
>This is now another user for the DEBUGCTL MSR; the access needs to be
>synchronized. I'll look into it.

I looked into the new block/single stepping support in
arch/x86/kernel/step.c.
It uses a TIF DEBUGCTLMSR and a field unsigned long debugctlmsr in
struct thread_struct.

When they are done stepping, they clear the TIF and the MSR.


Our patch uses a ds_area field in struct thread_struct and two TIF to
mark
the functionality, rather than the resource. We need to access the
DEBUGCTL
and DS_SAVE_AREA MSR's.

I would rewrite our patch to rename the TIF to name the used resource
and
move the code setting the DS_SAVE_AREA MSR to __switch_to_xtra; that
leaves
only the code to take the timestamp in ptrace_bts.c.


The two MSR accesses (or, rather, the two users of the TIF) still
conflict.
When either is done, he clears the TIF bit and thus disables the other
user.

I would introduce a convention:
- each user clears only the debugctl bits he used
- the TIF bit is cleared, if thread_struct.debugctlmsr == 0
- before setting any bit, each user first checks all bits he intends to
set
  if any is set already, he bails out with an error

Is there some better way to do this?


thanks and regards,
markus.
---------------------------------------------------------------------
Intel GmbH
Dornacher Strasse 1
85622 Feldkirchen/Muenchen Germany
Sitz der Gesellschaft: Feldkirchen bei Muenchen
Geschaeftsfuehrer: Douglas Lusk, Peter Gleissner, Hannes Schwaderer
Registergericht: Muenchen HRB 47456 Ust.-IdNr.
VAT Registration No.: DE129385895
Citibank Frankfurt (BLZ 502 109 00) 600119052

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/