Message-ID: <m1tzmuqr5u.fsf@ebiederm.dsl.xmission.com>
Date:	Fri, 07 Dec 2007 11:46:21 -0700
From:	ebiederm@...ssion.com (Eric W. Biederman)
To:	Neil Horman <nhorman@...hat.com>
Cc:	Vivek Goyal <vgoyal@...hat.com>,
	Neil Horman <nhorman@...driver.com>,
	Ben Woodard <woodard@...hat.com>,
	Andi Kleen <andi@...stfloor.org>, kexec@...ts.infradead.org,
	linux-kernel@...r.kernel.org, Andi Kleen <ak@...e.de>,
	hbabu@...ibm.com
Subject: Re: [PATCH] kexec: force x86_64 arches to boot kdump kernels on boot cpu

Neil Horman <nhorman@...hat.com> writes:

>> Does LAPIC allow to disable a specific vector and not accept interrupts? I
>> don't think so. If a timer interrupt is broadcasted to every cpu I think
>> everybody will accept it (like broadcast IPI). That's why intelligence
>> is built into IOAPIC and direct interrupts to a cpu or group of cpu.
>> 
> See disable_APIC_timer().  It seems to set the mask bit in the APIC_LVTT entry.

Yes.  The local allows us to choose to accept ExtInt interrupts or not.
We can't do it per vector but we can do by interrupt delivery path.
External Interrupt.
External NMI.
Logical Apic Bus (Although I don't know if we can disable this one).

>
>> I am just trying to understand the functionality better. Can somebody help me
>> understand how do we make sure that same timer interrupt is not processed by
>> all cpus (assuming hypertransport is broadcasting it)?
>> 
> I understand your desire, but clearly, something prevents it.  Note our earlier
> conversation, this bit doesn't actually force a unicast of an interrupt packet,
> but simply masks the destination field.  When set to zero, it simply means that
> the ht interrupt packet destination field is restricted to 4 bits rather than 8.
> So its not like when its set to zero we are guaranteed that it is forced to a
> single processor anyway.  All setting this bit does is ensure that if any apics
> out on a system are addresed using an extended apic id, that interrupts can
> reach them.  Thats why it was suggested that this bit only be forcibly set if
> bit 18 is also set.

We should only have a single cpus local apic configured to accept the
interrupt.  Further it would not surprise me if there was some first
come first served logic with accepting the interrupt in there
somewhere.


>> Again for my understanding, I got few questions.
>> 
>> - Why does nvidia choose not to broadcast the interrupts and still works
>>   fine? Does that mean nvidia chipse will not work the extended cpu apic
>>   ids?
>> 
> It doesn't! When booting normally getting interrupts to apics that use 4 bit
> apic ids is sufficient since cpu0 is in that set, but if we crash on a cpu with
> an extended id, we hang.

Yes.  This sounds like a BIOS bug at present.  A chipset feature
residing in the CPUs was not enabled properly.

>> - Why do I need to broadcast the interrupts and not target specific cpus?
>> 
> Its not a forced broadcast, its a mask on the apic id.  The IOAPIC still
> addresses specific cpus.

This is a broadcast for legacy mode interrupts which don't have a cpu
destination field.  Once we are running the timer through the ioapic
we have a destination field and the broadcast logic should not matter.

>> - If I am broadcasting interrupts, how do I make sure only one cpu
>>   picks it up.
>> 
> The IOAPIC handles that.

Well the local apics.   If you are in ioapic mode and give the
cpus a choice of which cpu to deliver to it is a hardware anycast irq
transmission.  That is the hardware magically picks one cpu of the
set of allow cpus to deliver the irq to.  How that happens is
implementation specific.

Eric
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