linux-kernel - RE: More info on port 80 symptoms on MCP51 machine.

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Message-ID: <F72FA20C31DD4F4C997B91C5B3690A090263BC96@hqemmail07.nvidia.com>
Date:	Sat, 15 Dec 2007 14:34:24 -0800
From:	"Allen Martin" <AMartin@...dia.com>
To:	"H. Peter Anvin" <hpa@...or.com>,
	"Alan Cox" <alan@...rguk.ukuu.org.uk>
Cc:	"Rene Herman" <rene.herman@...il.com>,
	"David P. Reed" <dpreed@...d.com>, "Pavel Machek" <pavel@....cz>,
	"Andi Kleen" <andi@...stfloor.org>,
	"linux-os (Dick Johnson)" <linux-os@...logic.com>,
	"David Newall" <david@...idnewall.com>,
	"Paul Rolland" <rol@...917.net>,
	"Krzysztof Halasa" <khc@...waw.pl>, <linux-kernel@...r.kernel.org>,
	"Thomas Gleixner" <tglx@...utronix.de>,
	"Ingo Molnar" <mingo@...hat.com>, <rol@...be.net>
Subject: RE: More info on port 80 symptoms on MCP51 machine.

> Alan Cox wrote:
> > On Wed, 12 Dec 2007 21:58:25 +0100
> > Rene Herman <rene.herman@...il.com> wrote:
> > 
> >> On 12-12-07 21:26, Rene Herman wrote:
> >>
> >>> On 12-12-07 21:07, David P. Reed wrote:
> >>>> Someone might have an in to nVidia to clarify this, 
> since I don't.  
> >>>> In any case, the udelay(2) approach seems to be a safe 
> fix for this machine.
> >> By the way, _does_ anyone have a contact at nVidia who 
> could clarify? 
> >> Alan maybe? I'm quite curious what they did...
> > 
> > I don't. Nvidia are not the most open bunch of people on 
> the planet. 
> > This doesn't appear to be a chipset bug anyway but a firmware one 
> > (other systems with the same chipset work just fine).
> > 
> > The laptop maker might therefore be a better starting point.
> 
> One wonders if it does some SMM trick to capture port 0x80 
> writes and attempt to haul them off for debugging; it almost 
> sounds like some kind of debugging code got let out into the field.
> 
> 	-hpa

Nothing inside the chipset should be decoding port 80 writes.  It's 
possible this board has a port 80 decoder wired onto the board that's 
misbehaving.  I've seen other laptop boards with port 80 decoders
wired onto the board, even if the 7 segment display is only populated
on debug builds.  

We use PCI port 80 decoders internally for debugging quite often, so 
if there were some chipset issue related to port 80 it would have 
showed up a long time ago, and this is the first I've heard of
hangs related to port 80 writes.

-Allen
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