linux-kernel - Re: [PATCH] x86: provide a DMI based port 0x80 I/O delay override

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Message-id: <4777E1CC.3080208@shaw.ca>
Date:	Sun, 30 Dec 2007 12:22:04 -0600
From:	Robert Hancock <hancockr@...w.ca>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	Alan Cox <alan@...rguk.ukuu.org.uk>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Rene Herman <rene.herman@...access.nl>, dpreed@...d.com,
	Islam Amer <pharon@...il.com>, hpa@...or.com,
	Pavel Machek <pavel@....cz>, Ingo Molnar <mingo@...hat.com>,
	Andi Kleen <andi@...stfloor.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: provide a DMI based port 0x80 I/O delay override

Ingo Molnar wrote:
> * Alan Cox <alan@...rguk.ukuu.org.uk> wrote:
> 
>>> i dont get your last point. Firstly, we do an "outb $0x80" not an 
>>> inb.
>> outb not inb sorry yes
>>
>>> Secondly, outb $0x80 has no PCI posting side-effects AFAICS. 
>>> Thirdly,
>> It does. The last mmio write cycle to the bridge gets pushed out 
>> before the 0x80 cycle goes to the PCI bridge, times out and goes to 
>> the LPC bus.
> 
> ok. Is it more of a "gets flushed due to timing out", or a 
> specified-for-sure POST flushing property of all out 0x80 cycles going 
> to the PCI bridge? I thought PCI posting policy is up to the CPU, it can 
> delay PCI space writes arbitrarily (within reasonable timeouts) as long 
> as no read is done from the _same_ IO space address. Note that the port 
> 0x80 cycle is neither a read, nor for the same address.

There's no guarantee in the spec that any IO access will flush pending 
MMIO writes. However, I suspect in the majority of implementations 
(perhaps all), it indeed does.

-- 
Robert Hancock      Saskatoon, SK, Canada
To email, remove "nospam" from hancockr@...pamshaw.ca
Home Page: http://www.roberthancock.com/

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