linux-kernel - Re: [PATCH] AMD Thermal Interrupt Support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Fri, 4 Jan 2008 23:26:37 +0100
From:	Andi Kleen <andi@...stfloor.org>
To:	Russell Leidich <rml@...gle.com>
Cc:	Andi Kleen <andi@...stfloor.org>,
	Torsten Kaiser <just.for.lkml@...glemail.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>, valdis.kletnieks@...edu,
	thockin@...gle.com
Subject: Re: [PATCH] AMD Thermal Interrupt Support

> As to the question of Athlon RevG, it turns out that it has the same
> thermal erratum as RevF.  Therefore the fact that this code only works
> with Barcelona and up is not a defficiency.

Thanks.

> 
> There are 2 pending issues, to which I have received insufficient feedback:
> 
> 1. Andi would like to eliminate the trampoline in mce_thermal.c, but
> no one has responded to my proposed disgusting hack on entry_64.S in
> order to do so.

There are two ways to do it: 

either duplicate the entry point in entry_64.S and set different
vectors or let the asm glue jump through a call vector (use 
apicinterrupt ...,*thermal_vector(%rip) ) Later is probably better.

> 
> 2. Ingo pointed out that a given config file did not build.  But when

The patch that was in git-x86 didn't build on 32bit. Perhaps it was a 
32bit config file? Run it under "linux32" or equivalent on your distro.

> +	 */
> +	if (therm_throt_process(1))
> +		mce_log_therm_throt_event(cpu, 1);
> +	/*
> +	 * We'll still get subsequent interrupts even if we don't clear the
> +	 * status bit in THERM_CTL_F3X64.  Take advantage of this fact to avoid
> +	 * touching PCI space.  (If this assumption fails at some point, we'll
> +	 * need to schedule_work() in order to enter a process context, so that
> +	 * PCI locks can be asserted for proper access.  This requirement, in

PCI locks are spinlocks so they don't need process context. In PREEMPT-RT
kernels they can sleep, but there the handler will be likely already
a thread. Touching config space from interrupt context is legal, although
not very popular because it tends to be slow (but a few drivers do it) 

> +	/*
> +	 * If any of the northbridges has PCI ID 0x1103, then its thermal
> +	 * hardware suffers from an erratum which prevents this code from
> +	 * working, so abort.

Please add 

 * This implies it only works on Family 10h aka AMD Quad Core.

Otherwise I can just see the support questions of people asking why this
doesn't work for them.

Anyways I'm unsure about the blacklist here -- white list would
probably have been better. k8_northbridges[] will certainly include
Griffin northtbridges and who knows if TT will work there or not.
[sorry for mentioning that not earlier]

-Andi
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/