[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <4787AD72.3080100@zytor.com>
Date: Fri, 11 Jan 2008 09:54:58 -0800
From: "H. Peter Anvin" <hpa@...or.com>
To: "David P. Reed" <dpreed@...d.com>
CC: Alan Cox <alan@...rguk.ukuu.org.uk>,
Rene Herman <rene.herman@...access.nl>,
Zachary Amsden <zach@...are.com>,
Christer Weinigel <christer@...nigel.se>,
Ondrej Zary <linux@...nbow-software.org>,
Bodo Eggert <7eggert@....de>, Ingo Molnar <mingo@...e.hu>,
Paul Rolland <rol@...917.net>, Pavel Machek <pavel@....cz>,
Thomas Gleixner <tglx@...utronix.de>,
linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...hat.com>,
rol <rol@...be.net>
Subject: Re: Re: [PATCH] x86: provide a DMI based port 0x80
I/O delay override.
David P. Reed wrote:
> Alan Cox wrote:
>>> bus abort on the LPC bus". More problematic is that I would think
>>> some people might want to turn on the AMD feature that generates
>>> machine checks if a bus timeout happens. The whole point of machine
>>> checks is
>>
>> An ISA/LPC bus timeout is fulfilled by the bridge so doesn't cause an
>> MCE.
> Good possibility, but the documentation on HyperTransport suggests
> otherwise, even for LPC bridges in this particular modern world of
> AMD64. I might do the experiment someday to see if my LPC bridge is
> implemented in a way that does or doesn't support enabling MCE's. Could
> be different between Intel and AMD - I haven't had reason to pore over
> the Intel chipset specs, since my poking into all this stuff has been
> driven by my personal machine's issues, and it's not got any Intel
> compatible parts.
If you have a subtractive decoding bridge you will have completion on HT.
-hpa
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists