lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20080125151017.GB11846@elte.hu>
Date:	Fri, 25 Jan 2008 16:10:17 +0100
From:	Ingo Molnar <mingo@...e.hu>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	Yinghai Lu <Yinghai.Lu@....COM>,
	Jeremy Fitzhardinge <jeremy@...p.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86: trim ram need to check if mtrr is there v3


* Andi Kleen <andi@...stfloor.org> wrote:

> Ingo Molnar <mingo@...e.hu> writes:
> >
> > what we should probably do instead is to have a filter function:
> >
> >    new_end = trim_range_to_mtrr_cached(start, end);
> >
> > and then we could iterate through every e820 map entry that is 
> > marked as usable RAM, and send it through this filter. If the filter 
> > returns the same value that got passed in, we keep the e820 entry 
> > unchanged. If the filter returns a new "end" value, we use that in 
> > the e820 map.
> 
> To be fully generic you would need to allow it to adjust start too.

no, to be fully generic it would have to be able to 'split' e820 entries 
up and punch holes into them - but we dont want to go that far i think. 
The most common problem is mismatch at the end of a range.

but what matters more is to have full, generic _detection_ of the 
problem - and that's what we dont do right now. (and that's what my 
reply outlines)

The _fixup_ which we base on this information can then be anything from 
"trivially trim the end" up to a complex "punch holes" solution or the 
simplest "print nasty warning message and do nothing else" solution.

> > that way, the current Tom2 hack is just a natural extension to the 
> > filter function: it would (on AMD CPUs) recognize (within 
> > trim_range_to_mtrr_cached filter) that all memory addresses above 
> > 4GB are marked as cacheable via Tom2.
> >
> > Or something like this. Hm?
> 
> I agree that would be the correct way to do it.
> 
> Later on with PAT that filter could also do PAT related checks and 
> something like this will likely be needed anyways.

a "what is the effective MTRR caching attribute of this physical 
address" type of function would benefit PAT too, yes.

	Ingo
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ