linux-kernel - [PATCH] atmel_spi: Fix clock polarity

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Date:	Thu, 21 Feb 2008 11:11:38 +0900 (JST)
From:	Atsushi Nemoto <anemo@....ocn.ne.jp>
To:	akpm@...ux-foundation.org
Cc:	David Brownell <david-b@...bell.net>,
	Haavard Skinnemoen <hskinnemoen@...el.com>,
	spi-devel-general@...ts.sourceforge.net,
	linux-kernel@...r.kernel.org
Subject: [PATCH] atmel_spi: Fix clock polarity

The atmel_spi driver does not initialize clock polarity correctly
(except for at91rm9200 CS0 channel) in some case.

The atmel_spi driver uses gpio-controlled chipselect.  OTOH spi clock
signal is controlled by CSRn.CPOL bit, but this register controls
clock signal correctly only in 'real transfer' duration.  At the time
of cs_activate() call, CSRn.CPOL will be initialized correctly, but
the controller do not know which channel is to be used next, so clock
signal will stay at the inactive state of last transfer.  If clock
polarity of new transfer and last transfer was differ, new transfer
will start with wrong clock signal state.

For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0
or 1 transfer, the clock signal state at the assertion of chipselect
will be low.  Of course this will violates SPI transfer.

This patch is short term solution for this problem.  It makes all
CSRn.CPOL match for the transfer before activating chipselect.  For
longer term, the best fix might be to let NPCS0 stay selected
permanently in MR and overwrite CSR0 with to the new slave's settings
before asserting CS.

Signed-off-by: Atsushi Nemoto <anemo@....ocn.ne.jp>
Acked-by: Haavard Skinnemoen <hskinnemoen@...el.com>
---
This patch is already in mm tree as atmel_spi-fix-clock-polarity.patch.
I just rewrite description slightly and add my signed-off and acked-by
from Haavard Skinnemoen.

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 293b7ca..85687aa 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -87,6 +87,16 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 	unsigned gpio = (unsigned) spi->controller_data;
 	unsigned active = spi->mode & SPI_CS_HIGH;
 	u32 mr;
+	int i;
+	u32 csr;
+	u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
+
+	/* Make sure clock polarity is correct */
+	for (i = 0; i < spi->master->num_chipselect; i++) {
+		csr = spi_readl(as, CSR0 + 4 * i);
+		if ((csr ^ cpol) & SPI_BIT(CPOL))
+			spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
+	}

 	mr = spi_readl(as, MR);
 	mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
--
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