linux-kernel - Re: [PATCH 1/3 v3] dma: document dma_{un}map_{single|sg}

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Sat, 1 Mar 2008 00:18:24 -0700
From:	Grant Grundler <grundler@...isc-linux.org>
To:	Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc:	James Bottomley <James.Bottomley@...senPartnership.com>,
	Grant Grundler <grundler@...isc-linux.org>,
	Michael Ellerman <michael@...erman.id.au>, akepner@....com,
	Tony Luck <tony.luck@...el.com>,
	Jesse Barnes <jbarnes@...tuousgeek.org>,
	Jes Sorensen <jes@....com>,
	Randy Dunlap <randy.dunlap@...cle.com>,
	Roland Dreier <rdreier@...co.com>,
	David Miller <davem@...emloft.net>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3 v3] dma: document dma_{un}map_{single|sg}_attrs()
	interface

On Sat, Mar 01, 2008 at 01:56:44PM +1100, Benjamin Herrenschmidt wrote:
...
> > This means that if ever anyone sets a PCIe bridge to relaxed ordering
> > by default, this attribute will also work for them.

Is this the same "relaxed ordering" defined in PCIe 1.0 specs?
If so, as explained before, use of "RO" bit in the DMA transactions
is up the the device and it MUST send a DMA transaction without
RO bit set to flush in-flight writes to the device. The host OS
does not have control over individual transactions, just the
general enablement of the feature. And "RO" bit should be
transperent to current applications including RDMA.

It's a very different issue than the SN2 node interconnect where
ALL transactions can be re-ordered by default and we have to do
something special to force ordering whene DMA writes are issued
to specific memory regions. The PCI device has no control over
this (unlike RO-bit discussed above).

hth,
grant

> But that would be asking for trouble no ? I would expect pretty much
> everything to break appart with relaxed by default no ? Or I don't fully
> understand what your arch calls "relaxed"...
> 
> I do agree that we should aim for simple semantics, they should cover
> 99% of the needs, and leave some bit space or attribute space for archs
> to define private ones when really needed.
> 
> In our case, I suspect that the two main thing we could define here for
> DMA that would be useful generally would be relaxed ordering (strict
> being the default) and maybe read prefetching (though that would be the
> default, maybe no prefetch). We -might- have use of separating relaxed
> ordering for read vs. writes, but that's pretty much it.
> 
> Cheers,
> Ben.
> 
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/