linux-kernel - Re: [patch] Re: using long instead of atomic

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Message-ID: <47D014A6.9090300@rtr.ca>
Date:	Thu, 06 Mar 2008 10:58:30 -0500
From:	Mark Lord <lkml@....ca>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	Alan Stern <stern@...land.harvard.edu>,
	Alan Cox <alan@...rguk.ukuu.org.uk>,
	Pavel Machek <pavel@....cz>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Zdenek Kabelac <zdenek.kabelac@...il.com>, davem@...emloft.net,
	"Rafael J. Wysocki" <rjw@...k.pl>,
	Pierre Ossman <drzeus-mmc@...eus.cx>,
	Kernel development list <linux-kernel@...r.kernel.org>,
	pm list <linux-pm@...ts.linux-foundation.org>
Subject: Re: [patch] Re: using long instead of atomic_t when only set/read
 is required

Linus Torvalds wrote:
> 
> On Mon, 3 Mar 2008, Alan Stern wrote:
>> Consider a routine like the following:
>>
>> 	static task_struct *the_task;
>>
>> 	void store_task(void)
>> 	{
>> 		the_task = current;
>> 	}
>>
>> Is it possible to say whether readers examining "the_task" are 
>> guaranteed to see a coherent value?
> 
> Yes, we do depend on this.  All the RCU stuff (and in general *anything* 
> that depends on memory ordering as opposed to full locking, and we have 
> quite a lot of it) is very fundamentally dependent on the fact that things 
> like pointers get read and written atomically.
..

But also consider something like this:

 	void store_task(void)
 	{
 		*the_task = current;
 	}

In this case, there is no guarantee that the assignment
can be done atomically on all CPU types.  Some RISC archs
(eg. MIPS R2xxx) require an (interruptible) instruction pair
to store values to a potentially unaligned address.

This was a BIG issue on a different system that I once worked on.

Cheers
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