| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <47E27D08.9050809@redhat.com> Date: Thu, 20 Mar 2008 12:04:40 -0300 From: Glauber Costa <gcosta@...hat.com> To: "Maciej W. Rozycki" <macro@...ux-mips.org> CC: linux-kernel@...r.kernel.org, akpm@...ux-foundation.org, tglx@...utronix.de, mingo@...e.hu, ak@...e.de Subject: Re: [PATCH 45/79] [PATCH] fix apic acking of irqs Maciej W. Rozycki wrote: > On Wed, 19 Mar 2008, Glauber de Oliveira Costa wrote: > >> EOI is a write-only register. Using write around will have the effect >> of reading it, which will make all subsequent reads of the ESR register >> to return an error code. It was unnotices for quite a while because main sources >> of reading the ESR register where done prior to apic interrupt enabling. > > Are you sure this actually triggers for APIC chips affected by the > erratum in question? And please note that for them the effect of two > consecutive writes will be much more disastrous than setting a bit in the > ESR register. > > Maciej I'm not _sure_, but I can't find anything in the errata list that states otherwise. It would be great that anyone has such a system to test it. But with the current conditions, it will break bootup code. In case it is really a problem, we'd need to make a special case for that. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists