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Date: Tue, 25 Mar 2008 10:42:19 -0700 (PDT) From: Christoph Lameter <clameter@....com> To: "Luck, Tony" <tony.luck@...el.com> cc: David Miller <davem@...emloft.net>, linux-mm@...ck.org, linux-kernel@...r.kernel.org, linux-ia64@...r.kernel.org Subject: RE: [11/14] vcompound: Fallbacks for order 1 stack allocations on IA64 and x86 On Mon, 24 Mar 2008, Luck, Tony wrote: > > I am familiar with that area and I am resonably sure that this > > is an issue on IA64 under some conditions (the processor decides to spill > > some registers either onto the stack or into the register backing store > > during tlb processing). Recursion (in the kernel context) still expects > > the stack and register backing store to be available. ccing linux-ia64 for > > any thoughts to the contrary. > > Christoph is correct ... IA64 pins the TLB entry for the kernel stack > (which covers both the normal C stack and the register backing store) > so that it won't have to deal with a TLB miss on the stack while handling > another TLB miss. I thought the only pinned TLB entry was for the per cpu area? How does it pin the TLB? The expectation is that a single TLB covers the complete stack area? Is that a feature of fault handling? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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