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Message-ID: <924EFEDD5F540B4284297C4DC59F3DEEC3E1EB@orsmsx423.amr.corp.intel.com>
Date:	Tue, 25 Mar 2008 16:38:22 -0700
From:	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>
To:	"Yinghai Lu" <yhlu.kernel@...il.com>,
	"H. Peter Anvin" <hpa@...or.com>
Cc:	"Ingo Molnar" <mingo@...e.hu>,
	"Thomas Gleixner" <tglx@...utronix.de>,
	"Andrew Morton" <akpm@...ux-foundation.org>,
	"kernel list" <linux-kernel@...r.kernel.org>,
	"Siddha, Suresh B" <suresh.b.siddha@...el.com>,
	"Barnes, Jesse" <jesse.barnes@...el.com>
Subject: RE: [PATCH] x86: pat cpu feature bit setting for known cpus

 

>-----Original Message-----
>From: Yinghai Lu [mailto:yhlu.kernel@...il.com] 
>Sent: Tuesday, March 25, 2008 4:09 PM
>To: H. Peter Anvin
>Cc: Ingo Molnar; Pallipadi, Venkatesh; Thomas Gleixner; Andrew 
>Morton; kernel list; Siddha, Suresh B
>Subject: Re: [PATCH] x86: pat cpu feature bit setting for known cpus
>
>On Tue, Mar 25, 2008 at 4:06 PM, H. Peter Anvin <hpa@...or.com> wrote:
>> Yinghai Lu wrote:
>>  >>
>>  >>  By the way, I want to clarify: I didn't mean it was 
>*intended* as
>>  >>  vendor-lockin, just that it's an undesirable effect of this.
>>  >
>>  > if the PAT works, we may need to trim the memory 
>according to MTRR, right?
>>  >
>>
>>  That doesn't seem like it's specific to PAT?
>
>could page table to  set WRBACK the range that is not covered 
>by MTRR in e820..
>

Trimming of e820 memory is already done by Jesse's patch here
commit 99fc8d424bc5d80
Are you referring to similar thing?

Thanks,
Venki

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