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Message-ID: <998d0e4a0803251647i2abefe96t34ec4ad6706afcfd@mail.gmail.com>
Date: Wed, 26 Mar 2008 00:47:16 +0100
From: "J.C. Pizarro" <jcpiza@...il.com>
To: "David Miller" <davem@...emloft.net>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: larger default page sizes...
On Tue, 25 Mar 2008 16:22:44 -0700 (PDT), David Miller wrote:
> > On Mon, 24 Mar 2008, David Miller wrote:
> >
> > > There are ways to get large pages into the process address space for
> > > compute bound tasks, without suffering the well known negative side
> > > effects of using larger pages for everything.
> >
> > These hacks have limitations. F.e. they do not deal with I/O and
> > require application changes.
>
> Transparent automatic hugepages are definitely doable, I don't know
> why you think this requires application changes.
>
> People want these larger pages for HPC apps.
But there is a general problem of larger pages in systems that
don't support them natively (in hardware) depending in how it's
implemented the memory manager in the kernel:
"Doubling the soft page size implies
halfing the TLB soft-entries in the old hardware".
"x4 soft page size=> 1/4 TLB soft-entries, ... and so on."
Assuming one soft double-sized page represents 2 real-sized pages,
one replacing of one soft double-sized page implies replacing
2 TLB's entries containing the 2 real-sized pages.
The TLB is very small, its entries are around 24 entries aprox. in
some processors!.
Assuming soft 64 KiB page using real 4 KiB pages => 1/16 TLB soft-entries.
If the TLB has 24 entries then calculating 24/16=1.5 soft-entries,
the TLB will have only 1 soft-entry for soft 64 KiB pages!!! Weird!!!
The normal soft sizes are 8 KiB or 16 KiB for non-native processors, not more.
So, the TLB of 24 entries of real 4 KiB will have 12 or 6
soft-entries respect.
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