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Message-ID: <ada63tw494z.fsf@cisco.com>
Date: Fri, 02 May 2008 15:46:20 -0700
From: Roland Dreier <rdreier@...co.com>
To: "Moore\, Eric" <Eric.Moore@....com>
Cc: <linux-kernel@...r.kernel.org>
Subject: Re: HELP: Is writeq an atomic operation??
> Is a 64bit write to MMIO registers an atomic operation when using the
> writeq API?
>
> My concern is when I send 64bit data via writeq, will it be sent out as
> two 32 bit writes? If so, is it possible that another CPU be sending
> the data at the same time. Meaning can I write the 1st 32bit data from
> CPU-A, meanwhile CPU-B is writing his 32bit data at the same time, and
> CPU-A didn't complete the full 64bit in one shot. If this could occur,
> is there an API that I can use to make sure the entire data sent in one
> atomic operation?
I don't have an authoritative answer, but I can say that I coded
drivers/infiniband/hw/mthca and .../mlx4 assuming that writeq() is
atomic in the sense that you say, and no one has reported any problems.
But I'm sure no one has stressed the drivers on 64-bit mips or anything
unusual like that.
- R.
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