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Date: Sun, 04 May 2008 08:37:22 +1000 From: Benjamin Herrenschmidt <benh@...nel.crashing.org> To: Roland Dreier <rdreier@...co.com> Cc: "Moore, Eric" <Eric.Moore@....com>, linux-kernel@...r.kernel.org Subject: Re: HELP: Is writeq an atomic operation?? On Fri, 2008-05-02 at 15:46 -0700, Roland Dreier wrote: > > Is a 64bit write to MMIO registers an atomic operation when using the > > writeq API? > > > > My concern is when I send 64bit data via writeq, will it be sent out as > > two 32 bit writes? If so, is it possible that another CPU be sending > > the data at the same time. Meaning can I write the 1st 32bit data from > > CPU-A, meanwhile CPU-B is writing his 32bit data at the same time, and > > CPU-A didn't complete the full 64bit in one shot. If this could occur, > > is there an API that I can use to make sure the entire data sent in one > > atomic operation? > > I don't have an authoritative answer, but I can say that I coded > drivers/infiniband/hw/mthca and .../mlx4 assuming that writeq() is > atomic in the sense that you say, and no one has reported any problems. > > But I'm sure no one has stressed the drivers on 64-bit mips or anything > unusual like that. Surely only on 64 bits archs right ? Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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