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Message-ID: <86802c440805071316p39b7f370u46fa4f36c420bce7@mail.gmail.com>
Date:	Wed, 7 May 2008 13:16:41 -0700
From:	"Yinghai Lu" <yhlu.kernel@...il.com>
To:	"Rene Herman" <rene.herman@...access.nl>
Cc:	"Daniel Hazelton" <dhazelton@...er.net>,
	"Ingo Molnar" <mingo@...e.hu>,
	"Linux Kernel" <linux-kernel@...r.kernel.org>, hpa@...or.com
Subject: Re: 2.6.26, PAT and AMD family 6

On Wed, May 7, 2008 at 1:06 PM, Rene Herman <rene.herman@...access.nl> wrote:
> On 07-05-08 21:39, Daniel Hazelton wrote:
>
>
> > HPA asked about why they used a whitelist instead of a blacklist in [1].
> The answer (in [2]) was that those are the CPU's that are guaranteed to
> properly support PAT (no known or potential errata). However in [3] Dean
> Gaudet complained about the AMD detection code having a limit that the Intel
> detection code did not.
> >
>
>  And in that thread both HPA and Ingo Molnar -- two of the three x86 arch
>  maintainers -- agreed that a whitelist is the wrong approach, with HPA
>  commenting that it lead to vendor lockin. And here I am talkng to an
>  Intel employee about why my entire AMD CPU family was excluded.
>
>  So why is this thing now in mainline with Ingo's sign-off and not a line
>  of changelog to explain it?
>
>
>
> >                     ^^^^^---- Here in Rene's patch...
> >
>
>  Yinghai's.
>
>
>
> > Wouldn't this be better if written the same as the Intel side, ie:
> > if (c->x86 >= 0xF && (c->x86 == 6 && c->x86_model == 7))
> > (or even with c->x86_model >= 7  ?)

i only can access opteron Rev E, Rev F, and Quad core. So i enabled that.

now, enable other one by one...

YH
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