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Date:	Thu, 15 May 2008 13:58:40 -0700
From:	Joel Becker <Joel.Becker@...cle.com>
To:	murtuja bharmal <murtuja_bharmal@...oo.com>
Cc:	Sam Ravnborg <sam@...nborg.org>, linux-kernel@...r.kernel.org,
	linux-kbuild <linux-kbuild@...r.kernel.org>
Subject: Re: Kbuild Makefile output

On Thu, May 15, 2008 at 07:31:31PM +0100, murtuja bharmal wrote:
> But now the problem is lots of file included in kernel
> module, compiled twice or even more then twice for
> user space (whithou kernel flag set) and kernel space
> as well.
> 
> Previously in 2.4 we use to put all output object file
> in different directories for kernel module and user
> binaries based on their compilation Flags.
> 
> Now after attaching kbuild makefile with this system,
> kbuild make all object file in source directory itself
> becasue of that userspace makefiles not able to
> compile those file again. Because one object file is
> already there by kbuild. So I am not able create
> userspace binary.

Two solutions.

1) Have the build name the output files appropritately.  That is,
compile foo.c to foo-kernel.o and foo-userspace.o.  Then link as needed.
The makefile dependencies Just Work.

2) Better - create a kbuild symlink farm.  That is, lay out your sources
however you want, but in a single directory that is not the parent put
your kbuild makefile.  Have it symlink all .c files for kernel building
into this directory.

toplevel
	dir1
		Makefile
		foo.c
	dir2
		Makefile
		bar.c
	dir3
		Makefile
		baz.c
	kbuild
		Makefile

The kbuild/Makefile does something like:

obj-$(CONFIG_MYMODULE) += mymodule.o
mymodule-objs := foo.o bar.o baz.o
mymodule-sources = $(patsubst %.o,%.c,$(mymodule-objs))

obj-sources = $(foreach obj,$(mymodule-sources),$(wildcard ../*/$(obj)))

$(mymodule-sources): $(obj-sources)
	for f in $(obj-sources); do	\
	  -ln -s $$f .;			\
	done

Joel

-- 

Life's Little Instruction Book #232

	"Keep your promises."

Joel Becker
Principal Software Developer
Oracle
E-mail: joel.becker@...cle.com
Phone: (650) 506-8127
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