linux-kernel - Re: MMIO and gcc re-ordering issue

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Message-ID: <20080602154812.GB2734@loki.buserror.net>
Date:	Mon, 2 Jun 2008 10:48:12 -0500
From:	Scott Wood <scottwood@...escale.com>
To:	Haavard Skinnemoen <haavard.skinnemoen@...el.com>
Cc:	Geert Uytterhoeven <geert@...ux-m68k.org>,
	benh@...nel.crashing.org, Matthew Wilcox <matthew@....cx>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	David Miller <davem@...emloft.net>, linux-arch@...r.kernel.org,
	linuxppc-dev@...abs.org, alan@...rguk.ukuu.org.uk,
	linux-kernel@...r.kernel.org, tpiepho@...escale.com
Subject: Re: MMIO and gcc re-ordering issue

On Mon, Jun 02, 2008 at 10:11:02AM +0200, Haavard Skinnemoen wrote:
> Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Fri, 30 May 2008, Haavard Skinnemoen wrote:
> > > Maybe we need another interface that does not do byteswapping but
> > > provides stronger ordering guarantees?
> > 
> > The byte swapping depends on the device/bus.
> 
> Of course. But isn't it reasonable to assume that a device integrated
> on the same silicon as the CPU is connected to a somewhat sane bus
> which doesn't require any byte swapping?

No, unfortunately. :-(

See the end of drivers/dma/fsldma.h.  Likewise with Freescale's PCI host
bridges; for some reason the bus itself being little endian led to the host
bridge control registers also being little endian.

-Scott
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