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Date: Fri, 06 Jun 2008 10:58:05 +0100
From: "Jan Beulich" <jbeulich@...ell.com>
To: "Jeremy Fitzhardinge" <jeremy@...p.org>
Cc: "Ingo Molnar" <mingo@...e.hu>, "Stable Kernel" <stable@...nel.org>,
<x86@...nel.org>,
"Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH UPDATED] x86: set PAE PHYSICAL_MASK_SHIFT to 44
bits.
Ah, yes!
Acked-By: Jan Beulich <jbeulich@...ell.com>
>>> Jeremy Fitzhardinge <jeremy@...p.org> 06.06.08 11:21 >>>
When a 64-bit x86 processor runs in 32-bit PAE mode, a pte can
potentially have the same number of physical address bits as the
64-bit host ("Enhanced Legacy PAE Paging"). This means, in theory,
we could have up to 52 bits of physical address in a pte.
The 32-bit kernel uses a 32-bit unsigned long to represent a pfn.
This means that it can only represent physical addresses up to 32+12=44
bits wide. Rather than widening pfns everywhere, just set 2^44 as the
Linux x86_32-PAE architectural limit for physical address size.
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@...rix.com>
Cc: Jan Beulich <jbeulich@...ell.com>
---
include/asm-x86/page_32.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
===================================================================
--- a/include/asm-x86/page_32.h
+++ b/include/asm-x86/page_32.h
@@ -22,7 +22,8 @@
#ifdef CONFIG_X86_PAE
-#define __PHYSICAL_MASK_SHIFT 36
+/* 44=32+12, the limit we can fit into an unsigned long pfn */
+#define __PHYSICAL_MASK_SHIFT 44
#define __VIRTUAL_MASK_SHIFT 32
#define PAGETABLE_LEVELS 3
--
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