linux-kernel - Re: Can Linux control PCIe Transaction Layer Packet creation, when writing to a region pointed to by Base Address Register

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <adaprqq8kep.fsf@cisco.com>
Date:	Mon, 09 Jun 2008 12:42:38 -0700
From:	Roland Dreier <rdreier@...co.com>
To:	"Meyers\, Jordan" <Jordan_Meyers@...le.comcast.com>
Cc:	<linux-kernel@...r.kernel.org>
Subject: Re: Can Linux control PCIe Transaction Layer Packet creation, when writing to a region pointed to by Base Address Register

 > Any thoughts or suggestions of how to ensure a buffer's data is
 > transferred from the driver to the PCIe card in a single TLP (where
 > the intended payload size is less than the max payload value in
 > Device Control register of the PCI register space)?

If you are doing MMIO (memory-mapped IO, that is, the CPU is using write
operations to write to a memory-mapped PCI BAR), then you probably
cannot ensure that the data goes into a single PCIe packet.  I think the
best you can do is map the PCI memory into the CPU's address space with
write combining (WC) enabled (see ioremap_wc() in recent kernels), which
is likely to generate larger bursts if possible.

 - R.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/