linux-kernel - Re: [PATCH 11/15] x86: move enabling of io_apic to prepare

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Message-ID: <86802c440806101249i3650aa59u1090110a803c3384@mail.gmail.com>
Date:	Tue, 10 Jun 2008 12:49:49 -0700
From:	"Yinghai Lu" <yhlu.kernel@...il.com>
To:	"Maciej W. Rozycki" <macro@...ux-mips.org>
Cc:	"Glauber Costa" <gcosta@...hat.com>, linux-kernel@...r.kernel.org,
	akpm@...ux-foundation.org, tglx@...utronix.de, mingo@...e.hu,
	hugh@...itas.com
Subject: Re: [PATCH 11/15] x86: move enabling of io_apic to prepare_cpus

On Tue, Jun 10, 2008 at 12:36 PM, Maciej W. Rozycki
<macro@...ux-mips.org> wrote:
> On Tue, 10 Jun 2008, Yinghai Lu wrote:
>
>> kernel should not assume io apic register is set right by firmware.
>
>  What is the basis of this assumption?  Linux generally assumes the
> chipset components have been placed by the firmware into a consistent
> state.  That does not necessarily mean suitable for Linux, hence the need
> to reconfigure a bit here or there, but there should be no need to touch
> components that are not going to be used by Linux directly.  The I/O APIC
> is no different.
>
>> and kernel actually doesn't trust them, and clear the io apic registers.
>
>  The I/O APIC registers are cleared, because this is the only way you can
> assure inconsistent configuration does not happen during reconfiguration.
> For example two inputs using the same vector or set up into the ExtINTA
> mode.  The original intent of the code was not to paper over breakage in
> the firmware.  You are trying to change it and it can be done, but it has
> to be justified well.
>
>> that patch just move that early before enable error vector.
>
>  What I am saying repeatedly is clearing of the I/O APIC is not guaranteed
> to happen for all the possible cases of Linux configuration.  Which means
> this is a partial solution only -- please try to propose a better one or
> provide the original problem report so that someone else can have a look
> at it.  What's triggering the error interrupt for example?  Is it
> recoverable?

ExtINT is routed to ioapic pin0. but the dst is set to 0.
and the systems has multi sockets with quadcore cpu, so the apic id of boot cpu
is set to 4 instead of 0

YH
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