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Message-Id: <1213155644.25745.60.camel@pasglop>
Date: Wed, 11 Jun 2008 13:40:44 +1000
From: Benjamin Herrenschmidt <benh@...nel.crashing.org>
To: Nick Piggin <nickpiggin@...oo.com.au>
Cc: Jesse Barnes <jbarnes@...tuousgeek.org>,
linux-arch@...r.kernel.org, Roland Dreier <rdreier@...co.com>,
James Bottomley <James.Bottomley@...senpartnership.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Matthew Wilcox <matthew@....cx>,
Trent Piepho <tpiepho@...escale.com>,
Russell King <rmk+lkml@....linux.org.uk>,
David Miller <davem@...emloft.net>, scottwood@...escale.com,
linuxppc-dev@...abs.org, alan@...rguk.ukuu.org.uk,
linux-kernel@...r.kernel.org
Subject: Re: MMIO and gcc re-ordering issue
On Wed, 2008-06-11 at 13:29 +1000, Nick Piggin wrote:
>
> Exactly, yes. I guess everybody has had good intentions here, but
> as noticed, what is lacking is coordination and documentation.
>
> You mention strong ordering WRT spin_unlock, which suggests that
> you would prefer to take option #2 (the current powerpc one): io/io
> is ordered and io is contained inside spinlocks, but io/cacheable
> in general is not ordered.
IO/cacheable -is- ordered on powepc in what we believe is the direction
that matter: IO reads are fully ordered vs. anything and IO writes are
ordered vs. previous cacheable stores. The only "relaxed" situation is
IO writes followed by cacheable stores, which I believe shouldn't be
a problem. (except for spinlocks for which we use the flag trick)
> I *would* prefer that io/cacheable actually is strongly ordered with
> the default accessors. Because if you have that, then the driver
> writer never has to care about memory ordering, provided they use
> correct locking for SMP issues. Same as x86. With option 2, there
> are still windows where you could possibly have issues.
>
> For any high performance drivers that are well maintained (ie. the
> ones where slowdown might be noticed), everyone should have a pretty
> good handle on memory ordering requirements, so it shouldn't take
> long to go through and convert them to relaxed accessors.
Ben.
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