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Message-ID: <20080815164213.GA29956@elte.hu>
Date:	Fri, 15 Aug 2008 18:42:13 +0200
From:	Ingo Molnar <mingo@...e.hu>
To:	Mark Langsdorf <mark.langsdorf@....com>
Cc:	Greg KH <greg@...ah.com>, Pavel Machek <pavel@...e.cz>,
	joachim.deguara@....com, gregkh@....cz, tglx@...utronix.de,
	mingo@...hat.com, hpa@...or.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 01/01][retry 5] x86: L3 cache index disable for 2.6.26


* Mark Langsdorf <mark.langsdorf@....com> wrote:

> New versions of AMD processors have support to disable parts
> of their L3 caches if too many MCEs are generated by the
> L3 cache.  
>    
> This patch provides a /sysfs interface under the cache
> hierarchy to display which caches indices are disabled
> (if any) and to monitoring applications to disable a
> cache index.
>    
> This patch does not set an automatic policy to disable
> the L3 cache.  Policy decisions would need to be made
> by a RAS handler.  This patch merely makes it easier to
> see what indices are currently disabled.

hm, looks good - but since i've got an earlier version of this included 
in -tip already:

 commit a24e8d36f5fc047dac9af6200322ed393f2e3175
 Author: Mark Langsdorf <mark.langsdorf@....com>
 Date:   Tue Jul 22 13:06:02 2008 -0500

    x86: L3 cache index disable for 2.6.26

could you please send a delta patch against tip/master?

   http://people.redhat.com/mingo/tip.git/README

Thanks,

	Ingo
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