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Date:	Sun, 17 Aug 2008 17:12:04 +0400
From:	Cyrill Gorcunov <gorcunov@...il.com>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	hpa@...or.com, tglx@...utronix.de, macro@...ux-mips.org,
	linux-kernel@...r.kernel.org,
	Suresh Siddha <suresh.b.siddha@...el.com>,
	"Pallipadi, Venkatesh" <venkatesh.pallipadi@...el.com>,
	Arjan van de Ven <arjan@...radead.org>
Subject: Re: one more apic merging preliminary series

[Ingo Molnar - Sun, Aug 17, 2008 at 02:45:40PM +0200]
| 
| * Cyrill Gorcunov <gorcunov@...il.com> wrote:
| 
| > Please review - any comments are welcome!
| > 
| > For now it's like code bloating - but it's just preliminary series to 
| > make apic_*.c code more or less similar. And it's still a bit far from 
| > being ready to be merged down.
| 
| applied to tip/x86/apic - thanks Cyrill.
| 
| Maciej's point about cleaning up the x2apic impact is very much true - 
| i've Cc:-ed Suresh and Venki. Even if we wont truly use x2apic in 32-bit 
| kernels, it's a piece of glue hardware that does not depend on which 
| mode the CPU is in, so support for it should be bitsize agnostic. It 
| will also obviously be good for test coverage, once x2apic capable hw 
| will be more widespread.
| 
| 	Ingo
| 

Thanks Ingo. I found a bit obscure point in APIC 32bit code -
disable_esr variable to be clear. Code reading didn't answer
me the question "for what is needed". 82489DX doesn't have ESR
register indeed I presumed that the variable is needed to set
'absence-flag' of a such register on some platform but it seems
the only code snippet where we use this flag is 32bit lapic_setup_esr.
Moreover others 32bit writers don't check for this feature but
just writting to ESR register...

		- Cyrill -
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