linux-kernel - Re: [PATCH] x86: smpboot - check if we have ESR register in wakeup_secondary

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Message-ID: <20080915140255.GC7131@lenovo>
Date:	Mon, 15 Sep 2008 18:02:55 +0400
From:	Cyrill Gorcunov <gorcunov@...il.com>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	"Maciej W. Rozycki" <macro@...ux-mips.org>,
	LKML <linux-kernel@...r.kernel.org>,
	Yinghai Lu <yhlu.kernel@...il.com>
Subject: Re: [PATCH] x86: smpboot - check if we have ESR register in
	wakeup_secondary_cpu

[Ingo Molnar - Mon, Sep 15, 2008 at 09:56:55AM +0200]
| 
| * Cyrill Gorcunov <gorcunov@...il.com> wrote:
| 
| > We should check if we have ESR register before writting to it.
| > 
| > Signed-off-by: Cyrill Gorcunov <gorcunov@...il.com>
| > ---
| > 
| > Please review!
| > it seems the same nit in do_boot_cpu - checking now.
| > 
| > Index: linux-2.6.git/arch/x86/kernel/smpboot.c
| > ===================================================================
| > --- linux-2.6.git.orig/arch/x86/kernel/smpboot.c	2008-09-14 19:43:03.000000000 +0400
| > +++ linux-2.6.git/arch/x86/kernel/smpboot.c	2008-09-14 21:49:36.000000000 +0400
| > @@ -598,10 +598,12 @@ wakeup_secondary_cpu(int logical_apicid,
| >  	 * Give the other CPU some time to accept the IPI.
| >  	 */
| >  	udelay(200);
| > -	maxlvt = lapic_get_maxlvt();
| > -	if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
| > -		apic_write(APIC_ESR, 0);
| > -	accept_status = (apic_read(APIC_ESR) & 0xEF);
| > +	if (APIC_INTEGRATED(apic_version[phys_apicid])) {
| > +		maxlvt = lapic_get_maxlvt();
| > +		if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
| > +			apic_write(APIC_ESR, 0);
| > +		accept_status = (apic_read(APIC_ESR) & 0xEF);
| > +	}
| >  	pr_debug("NMI sent.\n");
| 
| hm, is there any non-integrated lapic that has more than 3 lvts? iirc 
| lvts were introduced with the integrated lapic.
| 
| 	Ingo
| 

Ingo, here is an updated version of patch - only subject
and patch message updated (not patch body)

		- Cyrill -
---
From: Cyrill Gorcunov <gorcunov@...il.com>
Subject: x86: wakeup_secondary_cpu - check if we have ESR register to read

We shouldn't read ESR register on discrete APIC.
Check it first.

Signed-off-by: Cyrill Gorcunov <gorcunov@...il.com>
---

Index: linux-2.6.git/arch/x86/kernel/smpboot.c
===================================================================
--- linux-2.6.git.orig/arch/x86/kernel/smpboot.c	2008-09-14 19:43:03.000000000 +0400
+++ linux-2.6.git/arch/x86/kernel/smpboot.c	2008-09-14 21:49:36.000000000 +0400
@@ -598,10 +598,12 @@ wakeup_secondary_cpu(int logical_apicid,
 	 * Give the other CPU some time to accept the IPI.
 	 */
 	udelay(200);
-	maxlvt = lapic_get_maxlvt();
-	if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
-		apic_write(APIC_ESR, 0);
-	accept_status = (apic_read(APIC_ESR) & 0xEF);
+	if (APIC_INTEGRATED(apic_version[phys_apicid])) {
+		maxlvt = lapic_get_maxlvt();
+		if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
+			apic_write(APIC_ESR, 0);
+		accept_status = (apic_read(APIC_ESR) & 0xEF);
+	}
 	pr_debug("NMI sent.\n");
 
 	if (send_status)
--
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