linux-kernel - Re: [RFC PATCH 1/3] Unified trace buffer

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Message-ID: <alpine.LFD.1.10.0809241323590.3265@nehalem.linux-foundation.org>
Date:	Wed, 24 Sep 2008 13:30:15 -0700 (PDT)
From:	Linus Torvalds <torvalds@...ux-foundation.org>
To:	Martin Bligh <mbligh@...gle.com>
cc:	Peter Zijlstra <peterz@...radead.org>,
	Steven Rostedt <rostedt@...dmis.org>,
	linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	Andrew Morton <akpm@...ux-foundation.org>,
	prasad@...ux.vnet.ibm.com,
	Mathieu Desnoyers <compudj@...stal.dyndns.org>,
	"Frank Ch. Eigler" <fche@...hat.com>,
	David Wilder <dwilder@...ibm.com>, hch@....de,
	Tom Zanussi <zanussi@...cast.net>,
	Steven Rostedt <srostedt@...hat.com>
Subject: Re: [RFC PATCH 1/3] Unified trace buffer

On Wed, 24 Sep 2008, Martin Bligh wrote:
> 
> If we just record the TSC unshifted, in 27 bits, at 4GHz, that gives us
> about 1/30 of a second? So we either shift, use > 27 bits, or record
> at least 30 events a second, none of which I like much ...

No, we don't shift (we don't want to lose precision), and we don't use 
more than 27 bits by default.

the TSC at each entry should be a _delta_. It's the difference from the 
last one. And if you get less than 30 events per second, and you need a 
bigger difference, you insert an extra "sync" tracepoint that has a 59-bit 
thing (27 bits _plus_ the extra 'data').

Yes, it adds 8 bytes (assuming that minimal format), but it does so only 
for any trace event that is more than 1/30th of a second from its previous 
one. IOW, think of this not in bytes, but in bytes-per-second. It adds at 
most 8*30=240 bytes per second, but what it _saves_ is that when you have 
tens of thousands of events, it shaves 4 bytes FOR EACH EVENT.

See?

Also, quite often, the clock won't be running at 4GHz even if the CPU 
might. Intel already doesn't make the TSC be the nominal frequency, and 
other architectures with TSC's have long had the TSC be something like a 
"divide-by-16" clock rather than every single cycle because it's more 
power-efficient.

So there is often a built-in shift, and I doubt we'll see 10GHz TSC's even 
if we see 10GHz CPU's (which many people consider unlikely anyway, but 
I'm not going to bet against technology).

			Linus
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