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Message-ID: <B27EBC40D200ED48A3F4CC2EBEABAE0B16234BF4@orsmsx501.amr.corp.intel.com>
Date:	Wed, 1 Oct 2008 12:13:53 -0700
From:	"Allan, Bruce W" <bruce.w.allan@...el.com>
To:	Jiri Kosina <jkosina@...e.cz>
CC:	"Brandeburg, Jesse" <jesse.brandeburg@...el.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-netdev@...r.kernel.org" <linux-netdev@...r.kernel.org>,
	"kkeil@...e.de" <kkeil@...e.de>,
	"agospoda@...hat.com" <agospoda@...hat.com>,
	"arjan@...ux.intel.com" <arjan@...ux.intel.com>,
	"Graham, David" <david.graham@...el.com>,
	"Ronciak, John" <john.ronciak@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"chris.jones@...onical.com" <chris.jones@...onical.com>,
	"tim.gardner@...el.com" <tim.gardner@...el.com>,
	"airlied@...il.com" <airlied@...il.com>, Olaf Kirch <okir@...e.cz>
Subject: RE: [RFC PATCH 11/12] e1000e: write protect ICHx NVM to prevent
 malicious write/erase

On Wednesday, October 01, 2008 6:29 AM, Jiri Kosina wrote:
>
>Olaf raised a rather interesting question -- would iAMT be
>able to access
>NVM contents directly, even if the lock bit would be set on the device?
>I.e. is iAMT allowed direct access to the EEPROM contents, bypassing
>shadow ram mappings?
>
>Thanks,
>
>--
>Jiri Kosina
>SUSE Labs
>

Only write/erase accesses are blocked by hardware after the protected range and lockdown bits are set in this patch; reads are still allowed.  I just received confirmation that iAMT does not write to the GbE region of the NVM.
--
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