linux-kernel - RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part

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Message-ID: <A6AD88C3F2289247BE726C37303E1EB8844A6398@orsmsx505.amr.corp.intel.com>
Date:	Fri, 3 Oct 2008 17:53:04 -0700
From:	"Yu, Fenghua" <fenghua.yu@...el.com>
To:	Bjorn Helgaas <bjorn.helgaas@...com>
CC:	"Luck, Tony" <tony.luck@...el.com>,
	Jesse Barnes <jbarnes@...tuousgeek.org>,
	David Woodhouse <dwmw2@...radead.org>,
	Ingo Molnar <mingo@...e.hu>, Avi Kivity <avi@...hat.com>,
	Stephen Rothwell <sfr@...b.auug.org.au>,
	Andrew Morton <akpm@...ux-foundation.org>,
	LKML <linux-kernel@...r.kernel.org>,
	"linux-ia64@...r.kernel.org" <linux-ia64@...r.kernel.org>
Subject: RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel
 IOMMU: IA64 Specific Part

>> >This patch adds clflush_cache_range(), but it's not used anywhere.
>> Clflush_cache_range() is used in __iommu_flush_cache() in include/linux/intel-iommu.h.

>Oh, OK.  I didn't look hard enough to find __iommu_flush_cache()
> (currently in drivers/pci/intel-iommu.c).

>Architecturally, I'm surprised that ia64 would need to actually do a
>cache flush.  I would think the VT-d hardware would do coherent accesses
>which would make the cache flush unnecessary.

VT-d hardware supports both non cache coherency and cache coherency by bit Coherency in Extended Capabilities Register.

Could you please point me to the doc that explicitly says that architecturally ia64 doesn't need cache flush?

Thanks.

-Fenghua
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