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Date:	Thu, 09 Oct 2008 19:37:01 -0400
From:	Chris Snook <csnook@...hat.com>
To:	akataria@...are.com
CC:	Alok kataria <alokkataria1@...il.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jeff Hansen <x@...fhansen.com>,
	"torvalds@...ux-foundation.org" <torvalds@...ux-foundation.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"mingo@...e.hu" <mingo@...e.hu>
Subject: Re: [PATCH] Re: x86_32 tsc/pit and hrtimers

Alok Kataria wrote:
> On Thu, 2008-10-09 at 15:50 -0700, Chris Snook wrote:
>> Alok Kataria wrote:
>>> On Thu, 2008-10-09 at 14:03 -0700, Chris Snook wrote:
>>>
>>> I agree that in general this should be no, but since this is a
>>> commandline variable it will be normally set for only those systems
>>> which have only TSC as a option or know that the TSC is reliable.
>>> wouldn't doing this be ok for such systems ?
>> Hardware doesn't deliberately do any TSC synchronization, though you might get
>> it by accident in some configurations.  A VMware guest gets it for free thanks
>> to the hypervisor doing it in software, but we need to run the check when we're
>> booting on bare metal. 
> 
> The TSC sync algorithm right now expects that TSC are perfectly in sync
> between cpus.
> But, the hardware doesn't deliberately do any synchronization, so we can
> have situations where TSC was (accidently ? )off by a marginal value
> during boot and as a result we mark TSC as unstable and don't use it as
> a clocksource at all. For systems like the ones Jeff is using wouldn't
> that be a problem. IOW, even though the TSC was *marginally* off during
> bootup it should still be used as a clocksource, since you have no other
> option, no ? 

You seem to be conflating position and rate.  When we mark TSC as stable, we're 
saying it will always advance at a known rate on all CPUs, but this says nothing 
about the relative positions on the different CPUs.  That skew can be huge on 
some hardware, not just marginal, so we still need to synchronize them at boot 
time, even though we don't need to (and can't, in this case) verify stability 
with another continuous clock source.

-- Chris
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