linux-kernel - Re: dmaengine: DMA_CTRL

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Message-ID: <e9c3a7c20810131151q2d8c4b44ve538e00bc4d8ae1b@mail.gmail.com>
Date:	Mon, 13 Oct 2008 11:51:28 -0700
From:	"Dan Williams" <dan.j.williams@...el.com>
To:	"Sosnowski, Maciej" <maciej.sosnowski@...el.com>
Cc:	"Nicolas Ferre" <nicolas.ferre@...el.com>,
	"Linux Kernel list" <linux-kernel@...r.kernel.org>,
	"Haavard Skinnemoen" <hskinnemoen@...el.com>
Subject: Re: dmaengine: DMA_CTRL_ACK flag signification

On Tue, Oct 7, 2008 at 2:09 AM, Sosnowski, Maciej
<maciej.sosnowski@...el.com> wrote:
> Nicolas Ferre wrote:
>> Hi all,
>>
>> I am in the process of writing a driver for an on-chip Atmel DMA
>> engine.
>>
>> I am a little confused about the use of the flag DMA_CTRL_ACK : It
>> seems that it is set in most of the descriptors in use except the
>> first or last of a descriptor chain. So, I cannot find where this
>> flag is cleared. In short, I do not see what it is used for : how
>> must I take it into account in my driver (in device_prep_dma_memcpy()
>> for instance) ?
>>
>> Can you enlighten me ?
>>
>> Regards,
>
> Hi Nicolas,
>
> Sorry for the delay in response.
> Generally the idea behind DMA_CTRL_ACK is to let an application
> safely set a chain of dependent operations.
> What a DMA driver needs to do is to check
> if a given descriptor has been already acked (using async_tx_test_ack())
> before it recycles or releases it.
> You are right that there is no place where DMA_CTRL_ACK
> is cleared at the moment. I would say it is the offload engine driver
> responsibility to clear the flag when it recycles the descriptor.
> Dan, could you confirm?

It may be better to call this the 'ownership' bit as while it is clear
client code owns the descriptor and can add dependent operations, once
it is set the dmaengine driver is free to recycle the descriptor for
use in another operation.  The driver's only responsibility* is to
read the bit in its cleanup routine.

--
Dan

*Note that if the driver decides to support transfer sizes larger than
its hardware maximum then it needs to set the ack bit on any internal
descriptors.  I.e. if the hardware can only do 4KB per descriptor it
would allocate two descriptors for an 8KB transfer and set the ack bit
on the first, leaving the second up to the caller.
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