linux-kernel - Re: [RFC patch 05/15] get_cycles() : MIPS HAVE_GET_CYCLES

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Message-ID: <20081026101826.GB24378@linux-mips.org>
Date:	Sun, 26 Oct 2008 10:18:26 +0000
From:	Ralf Baechle <ralf@...ux-mips.org>
To:	Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Ingo Molnar <mingo@...e.hu>, linux-kernel@...r.kernel.org,
	linux-arch@...r.kernel.org, Steven Rostedt <rostedt@...dmis.org>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Thomas Gleixner <tglx@...utronix.de>,
	David Miller <davem@...emloft.net>,
	Ingo Molnar <mingo@...hat.com>
Subject: Re: [RFC patch 05/15] get_cycles() : MIPS HAVE_GET_CYCLES_32

On Thu, Oct 16, 2008 at 07:27:34PM -0400, Mathieu Desnoyers wrote:

> partly reverts commit efb9ca08b5a2374b29938cdcab417ce4feb14b54. Selects
> HAVE_GET_CYCLES_32 only on CPUs where it is safe to use it.
> 
> Currently consider the "_WORKAROUND" cases for 4000 and 4400 to be unsafe, but
> should probably add other sub-architecture to the blacklist.
> 
> Do not define HAVE_GET_CYCLES because MIPS does not provide 64-bit tsc (only
> 32-bits).

[...]

> Index: linux-2.6-lttng/include/asm-mips/timex.h
> ===================================================================
> --- linux-2.6-lttng.orig/include/asm-mips/timex.h	2008-10-16 12:25:47.000000000 -0400
> +++ linux-2.6-lttng/include/asm-mips/timex.h	2008-10-16 12:34:18.000000000 -0400
> @@ -29,14 +29,39 @@
>   * which isn't an evil thing.
>   *
>   * We know that all SMP capable CPUs have cycle counters.
> + *
> + * Mathieu Desnoyers <mathieu.desnoyers@...ymtl.ca>
> + * HAVE_GET_CYCLES makes sure that this case is handled properly :
> + *
> + * Ralf Baechle <ralf@...ux-mips.org> :
> + * This avoids us executing an mfc0 c0_count instruction on processors which
> + * don't have but also on certain R4000 and R4400 versions where reading from
> + * the count register just in the very moment when its value equals c0_compare
> + * will result in the timer interrupt getting lost.
>   */

The usual workaround for this processor bug is to check if the value of
the c0_count and c0_compare registers are close.  Clone, not identical to
allow for the time skew in the pipeline.  If they are close, then
execute the timer interrupt handler.  See also the R4000/R4400 errata.

  Ralf
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