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Message-ID: <20081104165811.GA1664@elte.hu>
Date: Tue, 4 Nov 2008 17:58:11 +0100
From: Ingo Molnar <mingo@...e.hu>
To: Cyrill Gorcunov <gorcunov@...il.com>
Cc: Alexander van Heukelum <heukelum@...tmail.fm>,
Alexander van Heukelum <heukelum@...lshack.com>,
LKML <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
"H. Peter Anvin" <hpa@...or.com>, lguest@...abs.org,
jeremy@...source.com, Steven Rostedt <srostedt@...hat.com>,
Mike Travis <travis@....com>,
Jeremy Fitzhardinge <jeremy@...p.org>,
Andi Kleen <andi@...stfloor.org>
Subject: Re: [PATCH RFC/RFB] x86_64, i386: interrupt dispatch changes
* Cyrill Gorcunov <gorcunov@...il.com> wrote:
> [Alexander van Heukelum - Tue, Nov 04, 2008 at 05:23:09PM +0100]
> ...
> |
> | I did some timings using the little program below (32-bit only), doing
> | 1024 times the same sequence. TEST1 is just pushing a constant onto
> | the stack; TEST2 is pushing the cs register; TEST3 is the sequence
> | from the patch to extract the vector number from the cs register.
> |
> | Opteron (cycles): 1024 / 1157 / 3527
> | Xeon E5345 (cycles): 1092 / 1085 / 6622
> | Athlon XP (cycles): 1028 / 1166 / 5192
>
> Xeon is defenitely out of luck :-)
it's still OK - i.e. no outrageous showstopper overhead anywhere in
that instruction sequence. The total round-trip overhead is what will
matter most.
Ingo
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