linux-kernel - Re: [patch 0/3] [Announcement] Performance Counters for Linux

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Message-ID: <18751.33074.432802.639068@harpo.it.uu.se>
Date:	Wed, 10 Dec 2008 09:43:30 +0100
From:	Mikael Pettersson <mikpe@...uu.se>
To:	Paul Mundt <lethal@...ux-sh.org>
Cc:	David Miller <davem@...emloft.net>, andi@...stfloor.org,
	mingo@...e.hu, a.p.zijlstra@...llo.nl, paulus@...ba.org,
	tglx@...utronix.de, linux-kernel@...r.kernel.org,
	linux-arch@...r.kernel.org, akpm@...ux-foundation.org,
	eranian@...glemail.com, dada1@...mosbay.com,
	robert.richter@....com, arjan@...radead.org, hpa@...or.com,
	rostedt@...dmis.org
Subject: Re: [patch 0/3] [Announcement] Performance Counters for Linux

Paul Mundt writes:
 > The sh perf counters were not designed with overflowing in mind, they are
 > split in to a pair of 48-bit or 64-bit counters that simply keep running.
 > Any write simply clears the value and the counter starts over. They are
 > simply counters only, and generate no events whatsoever.
 > 
 > Oprofile has been a pretty bad fit for them, and while I'm slightly more
 > optimistic about perfmon, I'm rather less enthusiastic about yet another
 > peformance counter implementation that I am unable to make any use of. 

My 'perfctr' kernel extension has supported this type of hardware
since its beginning in 1999, simply because that's how much hardware
worked at the time. Typical CPUs in that category include Intel P5s,
Intel P6s where the local APIC isn't available (some don't have one
in HW, many have it disabled by BIOS), 1st gen AMD K7, VIA C3, early
UltraSPARCs (not supported by perfctr but could be), and many G3/G4
type 32-bit PowerPCs where HW errata make the PMU overflow interrupt
facility useless or dangerous.

Plain event counting over a group of counters is a convenient way of
computing metrics for isolated blocks of code, such as CPI, branch
misses / insn or clock, and such, so I often use that even on CPUs
that do support overflow interrupts.
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