linux-kernel - Re: [patch] Performance Counters for Linux, v3

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Date:	Thu, 11 Dec 2008 13:02:33 -0500 (EST)
From:	Vince Weaver <vince@...ter.net>
To:	Ingo Molnar <mingo@...e.hu>
Cc:	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Stephane Eranian <eranian@...glemail.com>,
	Eric Dumazet <dada1@...mosbay.com>,
	Robert Richter <robert.richter@....com>,
	Arjan van de Veen <arjan@...radead.org>,
	Peter Anvin <hpa@...or.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>,
	"David S. Miller" <davem@...emloft.net>
Subject: Re: [patch] Performance Counters for Linux, v3

Can someone tell me which performance counter implementation is likely to 
get merged into the Kernel?

I have at least 60 machines that I do regular performance counter work on. 
They involve Pentium Pro, Pentium II, 32-bit Athlon, 64-bit Athlon, 
Pentium 4, Pentium D, Core, Core2, Atom, MIPS R12k, Niagara T1, 
and PPC/Playstation 3.

Perfmon3 works for all of those 60 machines.  This new proposal works on a 
2 out of the 60.

Who is going to add support for all of those machines?  I've spent a lot 
of developer time getting prefmon going for all of those configurations. 
But why should I help out with this new inferior proposal?  It could all 
be another waste of time.

So I'd like someone to commit to some performance monitoring architecture. 
Otherwise we're going to waste thousands of hours of developer time around 
the world.  It's all pointless.

Also, my primary method of using counters is total aggregate count for a 
single user-space process.  So I use perfmon's pfmon tool to run an entire 
lon-running program, gathering full stats only at the very end.  pfmon can 
do this with pretty much zero overhead (I have lots of data and a few 
publications using this method).  Can this new infrastructure to this?  I 
find the documentation/tools support to be very incomplete.

One comment on the patch.

> +	/*
> +	 * Common hardware events, generalized by the kernel:
> +	 */
> +	PERF_COUNT_CYCLES		=  0,
> +	PERF_COUNT_INSTRUCTIONS		=  1,
> +	PERF_COUNT_CACHE_REFERENCES	=  2,
> +	PERF_COUNT_CACHE_MISSES		=  3,
> +	PERF_COUNT_BRANCH_INSTRUCTIONS	=  4,
> +	PERF_COUNT_BRANCH_MISSES	=  5,

Many machines do not support these counts.  For example, Niagara T1 does 
not have a CYCLES count.  And good luck if you think you can easily come 
up with something meaningful for the various kind of CACHE_MISSES on the 
Pentium 4.  Also, the Pentium D has various flavors of retired instruction 
count with slightly different semantics.  This kind of abstraction should 
be done in userspace.

Vince
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