linux-kernel - Re: [patch] Performance Counters for Linux, v3

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Date:	Fri, 12 Dec 2008 10:07:23 +0100
From:	Ingo Molnar <mingo@...e.hu>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	eranian@...il.com, Vince Weaver <vince@...ter.net>,
	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Eric Dumazet <dada1@...mosbay.com>,
	Robert Richter <robert.richter@....com>,
	Arjan van de Veen <arjan@...radead.org>,
	Peter Anvin <hpa@...or.com>, Paul Mackerras <paulus@...ba.org>,
	"David S. Miller" <davem@...emloft.net>
Subject: Re: [patch] Performance Counters for Linux, v3


* Peter Zijlstra <peterz@...radead.org> wrote:

> On Fri, 2008-12-12 at 09:51 +0100, Peter Zijlstra wrote:
> > On Fri, 2008-12-12 at 09:35 +0100, stephane eranian wrote:
> > > Peter,
> > > 
> > > On Fri, Dec 12, 2008 at 9:25 AM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
> > > >> > +   /*
> > > >> > +    * Common hardware events, generalized by the kernel:
> > > >> > +    */
> > > >> > +   PERF_COUNT_CYCLES               =  0,
> > > >> > +   PERF_COUNT_INSTRUCTIONS         =  1,
> > > >> > +   PERF_COUNT_CACHE_REFERENCES     =  2,
> > > >> > +   PERF_COUNT_CACHE_MISSES         =  3,
> > > >> > +   PERF_COUNT_BRANCH_INSTRUCTIONS  =  4,
> > > >> > +   PERF_COUNT_BRANCH_MISSES        =  5,
> > > >>
> > > >> Many machines do not support these counts.  For example, Niagara T1 does
> > > >> not have a CYCLES count.  And good luck if you think you can easily come
> > > >> up with something meaningful for the various kind of CACHE_MISSES on the
> > > >> Pentium 4.  Also, the Pentium D has various flavors of retired instruction
> > > >> count with slightly different semantics.  This kind of abstraction should
> > > >> be done in userspace.
> > > >
> > > > I'll argue to disagree, sure such events might not be supported by any
> > > > particular hardware implementation - but the fact that PAPI gives a list
> > > > of 'common' events means that they are, well, common. So unifying them
> > > > between those archs that do implement them seems like a sane choice, no?
> > > >
> > > > For those archs that do not support it, it will just fail to open. No
> > > > harm done.
> > > >
> > > > The proposal allows for you to specify raw hardware events, so you can
> > > > just totally ignore this part of the abstraction.
> > > >
> > > I believe the cache related events do not belong in here. There is no definition
> > > for them. You don't know what cache miss level, what kind of access. You cannot
> > > do this even on Intel Core processors.
> > 
> > I might agree with that, perhaps we should model this to the common list
> > PAPI specifies?
> 
> http://icl.cs.utk.edu/projects/papi/files/html_man3/papi_presets.html
> 
> Has a lot of cache events.
> 
> And I can see the use of a set without the L[123] in there, which would 
> signify either all or the lack of more specific knowledge. Like with 
> PAPI its perfectly fine to not support these common events on a 
> particular hardware platform.

yes, exactly.

A PAPI wrapper on top of this code might even opt to never use any of the 
generic types, because it can be well aware of all the CPU types and 
their exact event mappings to raw types, and can use those directly.

Different apps like KernelTop might opt to utilize the generic types.

A kernel is all about providing intelligent, generalized access to hw 
resources.

	Ingo
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