linux-kernel - Re: [RFC PATCH crypto] AES: Add support to Intel AES-NI instructions

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Message-Id: <E1LClB3-0006WP-9J@gondolin.me.apana.org.au>
Date:	Wed, 17 Dec 2008 12:26:17 +1100
From:	Herbert Xu <herbert@...dor.apana.org.au>
To:	ying.huang@...el.com (Huang Ying)
Cc:	herbert@...dor.apana.org.au, suresh.b.siddha@...el.com,
	linux-crypto@...breakpoint.cc, akpm@...ux-foundation.org,
	linux-kernel@...r.kernel.org, linux-crypto@...r.kernel.org,
	mingo@...e.hu, tglx@...utronix.de
Subject: Re: [RFC PATCH crypto] AES: Add support to Intel	AES-NI	instructions

Huang Ying <ying.huang@...el.com> wrote:
>
> f. if TS is clear, then use x86_64 implementation. Otherwise if
> user-space has touched the FPU, we save the state, if not then simply
> clear TS.

Well I'd rather avoid using the x86_64 implementation ever because
unless the chip guys have really screwed up we should be looking at
a difference of at least a factor of 10.

BTW I wasn't very clear in the original email.  You'd only do the
asynchronous operation for CBC/ECB.  For the simple AES case I
suppose we'll just have to stick to the x86_64 fallback.  This'll
really suck for disk encryption but I guess you could always add
an LRW/XTS mode to your code.

Cheers,
-- 
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@...dor.apana.org.au>
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