linux-kernel - Re: [Perfctr-devel] [patch] Performance Counters for Linux, v4

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Message-ID: <20081217015601.GE5147@const.famille.thibault.fr>
Date:	Wed, 17 Dec 2008 02:56:01 +0100
From:	Samuel Thibault <samuel.thibault@...-lyon.org>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	William Cohen <wcohen@...hat.com>, Ingo Molnar <mingo@...e.hu>,
	linux-kernel@...r.kernel.org,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	"David S. Miller" <davem@...emloft.net>,
	Robert Richter <robert.richter@....com>,
	Eric Dumazet <dada1@...mosbay.com>,
	Stephane Eranian <eranian@...glemail.com>,
	Paul Mackerras <paulus@...ba.org>, Peter Anvin <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Andrew Morton <akpm@...ux-foundation.org>,
	perfctr-devel@...ts.sourceforge.net,
	Arjan van de Ven <arjan@...radead.org>
Subject: Re: [Perfctr-devel] [patch] Performance Counters for Linux, v4

Andi Kleen, le Wed 17 Dec 2008 02:51:54 +0100, a écrit :
> William Cohen <wcohen@...hat.com> writes:
> > PERF_COUNT_CACHE_REFERENCES and PERF_COUNT_CACHE_MISSES are not single
> > monolitic events on many processors. There are multiple cache
> > levels. The L1 cache most processors have separate instruction and
> > data caches and require multiple counters to implement. Would these
> > refer to the last level of cache before memory and just be used to
> > compute the hit/miss rate for that last level? Some processors in the
> > same family have L2 and some processors have L3 cache. The setup code
> > would need to distinguish between these processor variants.
> 
> The difference between L1 and L3 caches can be huge (in some cases
> two orders of magnitude). With that I'm not sure a single cache
> miss/hit event even makes any sense.

Confirmed.  I have a code for which I'd like to know whether it fits
into at least L2 or even L1.

Samuel
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