linux-kernel - Re: [PATCH] dmatest: flush and invalidate destination buffer before DMA

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Message-Id: <20090106.101425.109407744.nemoto@toshiba-tops.co.jp>
Date:	Tue, 06 Jan 2009 10:14:25 +0900 (JST)
From:	Atsushi Nemoto <anemo@....ocn.ne.jp>
To:	dan.j.williams@...el.com
Cc:	anemo@....ocn.ne.jp, haavard.skinnemoen@...el.com,
	linux-kernel@...r.kernel.org, hskinnemoen@...el.com,
	maciej.sosnowski@...el.com, ralf@...ux-mips.org
Subject: Re: [PATCH] dmatest: flush and invalidate destination buffer
 before DMA

On Mon, 5 Jan 2009 11:31:57 -0700, "Dan Williams" <dan.j.williams@...el.com> wrote:
> > On nono-coherent MIPS platforms, dma_map_single() for DMA_TO_DEVICE
> > writeback the cache, dma_map_single() for DMA_FROM_DEVICE invalidated
> > (without writeback) the cache.  dma_unmap_simgle() is a nop.
> >
> > If dst_off was not cacheline aligned, dma_map_single(...,
> > DMA_FROM_DEVICE) in dma_async_memcpy_buf_to_buf() invalidate whole
> > cachelines including dst_off.  So, for example, the initialized data
> > at dst_off - 1 will be just discarded.  This result mismatch error of
> > course.  Same error can be happen at end of the real DMA area.
> >
> > I added dma_map_single/dma_unmap_single to just flush all dstbuf to
> > main memory.
> 
> I am tempted to say this is a bug in the MIPS dma_map_single
> implementation.  It is at least a difference in behavior from ARM
> where partial cachelines are cleaned+invalidated in the
> DMA_FROM_DEVICE case [1].

Yes, MIPS and ARM do different thing on partial cache line.  But I
suppose this belongs to "implementation dependent" area of DMA API so
users of the API should not depend on it.  (Well, maybe I'm biased to
MIPS ;-))

In general, drivers must not put normal data and DMA buffer on same
cacheline anyway to avoid unexpected writeback and data loss.  So this
ambiguity is not a problem.  IMHO writeback of the partial line for
DMA_FROM_DEVICE just _hides_ abusing of the DMA API and potential data
loss.

---
Atsushi Nemoto
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