linux-kernel - Re: [PATCH] dmatest: flush and invalidate destination buffer before DMA

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Message-ID: <20090109222721.GA3618@flint.arm.linux.org.uk>
Date:	Fri, 9 Jan 2009 22:27:21 +0000
From:	Russell King <rmk+lkml@....linux.org.uk>
To:	Ralf Baechle <ralf@...ux-mips.org>
Cc:	Haavard Skinnemoen <haavard.skinnemoen@...el.com>,
	linux-arch@...r.kernel.org, Atsushi Nemoto <anemo@....ocn.ne.jp>,
	dan.j.williams@...el.com, linux-kernel@...r.kernel.org,
	maciej.sosnowski@...el.com
Subject: Re: [PATCH] dmatest: flush and invalidate destination buffer before DMA

On Fri, Jan 09, 2009 at 11:19:36AM +0000, Ralf Baechle wrote:
> On Thu, Jan 08, 2009 at 09:36:03AM +0100, Haavard Skinnemoen wrote:
> > In the general case, however, I think MIPS has a bug: I've seen drivers
> > DMA to/from tiny buffers stored inside another struct. This is legal
> > because the driver can guarantee that the other fields in the struct
> > aren't accessed in the mean time, but any fields sharing a cacheline
> > with the buffer must be written back before the lines are invalidated.
> 
> Depending on the implementation details, the use of such a struct might be
> relying on implementation-specific behaviour.  This is what
> Documentation/DMA-API.txt has to say:
> 
> [...]
> int
> dma_get_cache_alignment(void)
> 
> Returns the processor cache alignment.  This is the absolute minimum
> alignment *and* width that you must observe when either mapping
> memory or doing partial flushes.
> 
> Notes: This API may return a number *larger* than the actual cache
> line, but it will guarantee that one or more cache lines fit exactly
> into the width returned by this call.  It will also always be a power
> of two for easy alignment.
> [...]
> 
> Since dma_get_cache_alignment() is a function not a constant its result
> can't be used in the definition of a struct unless possibly excessive
> padding is used.
> 
> The debate has shown that we problably need BUG_ON() assertions in the
> DMA API implementations to catch this sort of dangerous use.

I really don't think that's a realistic option.  You're asking for
every call to the DMA API to ensure that the buffer and length are
a multiple of the cache line size.

So, what happens if, eg, SPI wants to send a 16 byte buffer, and your
cache lines are 64 bytes?  Does the SPI driver have to kmalloc a new
chunk of memory 64 bytes long and copy the data into that before
passing it into the DMA API?

If you start enforcing that kind of thing, I think the cache coherent
people will take violent exception and refuse to play such games - and
quite rightly so.

-- 
Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:
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