linux-kernel - Re: regarding the x86_64 zero-based percpu patches

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Message-ID: <Pine.LNX.4.64.0901121258480.3101@quilx.com>
Date:	Mon, 12 Jan 2009 13:00:46 -0600 (CST)
From:	Christoph Lameter <cl@...ux-foundation.org>
To:	"Eric W. Biederman" <ebiederm@...ssion.com>
cc:	Rusty Russell <rusty@...tcorp.com.au>, Tejun Heo <tj@...nel.org>,
	Ingo Molnar <mingo@...e.hu>, travis@....com,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	Andrew Morton <akpm@...ux-foundation.org>, steiner@....com,
	Hugh Dickins <hugh@...itas.com>
Subject: Re: regarding the x86_64 zero-based percpu patches

On Mon, 12 Jan 2009, Eric W. Biederman wrote:

> > There are 2M TLB entries on x86_64. If we really get into a high usage
> > scenario then the 2M entry makes sense. Average server memory sizes likely
> > already are way beyond 10G per box. The higher that goes the more
> > reasonable the 2M TLB entry will be.
>
> 2M of per cpu data doesn't make sense, and likely indicates a design
> flaw somewhere.  It just doesn't make sense to have large amounts of
> data allocated per cpu.

Some data is not small. MIB data is allocated per cpu etc etc

> What would be better is simply to:
> - Require a lock to access another cpus per cpu data.
> - Do large page allocations for the per cpu data.
>
> At which point we could grow the per cpu data by simply reallocating it on
> each cpu and updating the register that holds the base pointer.

If per cpu data areas have no fixed address then you cannot use list
operations on per cpu data nor can the address of per cpu variables be
stored anywhere.

But maybe that is okay?

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